ASIC RTL Design Engineer, Platforms

Employment Type

: Full-Time


: Engineering

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

You're an experienced ASIC RTL design engineer for advanced ASIC chip development, and you'll work on our memory subsystem design team. You'll work as an individual contributor and you'll be tasked with driving the micro-architecture and RTL design for components of a high performance memory subsystem.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.


  • Engage with other chip architects and at the SoC level to drive thearchitectural definition of the memory subsystem.
  • Engage with 3rd party IP providers to evaluate against architectural goals, relative merits of memory controller and PHY IPs and to lead and drive integration of IPs.
  • Partner with the physical design team to resolve implementation level details and tradeoffs.
  • Work closely with design-for-test, design verification, emulation teams to test and ensure proper functionality.
  • Deliver quality micro-architectural level documentation and RTL code meeting project Power/Performance/Area (PPA) and schedule goals.

  • Minimum qualifications:

  • Bachelor's degree in Electrical/Computer Engineering, Computer Science or related field.
  • 3 years of experience in research and/or development of memory or interconnected system architectures.
  • 3 years of RTL and micro-architecture design experience.

  • Preferred qualifications:

  • Experience in memory subsystems and/or on-chip interconnect systems modeling.
  • Experience in characterizing performance, doing comparison studies, and documenting and publishing results.
  • Experience with DRAM interface calibration/training mechanisms and algorithms.
  • Experience in emulation.
  • Knowledge of high performance memory subsystem, including DRAM controller design, PHY architecture and design and DFI interface.
  • * The salary listed in the header is an estimate based on salary data for similar jobs in the same area. Salary or compensation data found in the job description is accurate.

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